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PRELIMINARY
Notice: This is not a final specification. Some parametric limits are subject to change.
R8C/2K Group, R8C/2L Group
RENESAS MCU
REJ03B0219-0010 Rev.0.10 Jul 20, 2007
1.
1.1
Overview
Features
The R8C/2K Group and R8C/2L Group of single-chip MCUs incorporates the R8C/Tiny Series CPU core, employing sophisticated instructions for a high level of efficiency. With 1 Mbyte of address space and is capable of executing instructions at high speed. In addition, the CPU core boasts a multiplier for high-speed operation processing. Power consumption is low, and the supported operating modes allow additional power control. These MCUs also use an anti-noise configuration to reduce emissions of electromagnetic noise and are designed to withstand EMI. Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of system components. Furthermore, the R8C/2L Group has on-chip data flash (1 KB x 2 blocks). The difference between the R8C/2K Group and R8C/2L Group is only the presence or absence of data flash. Their peripheral functions are the same.
1.1.1
Applications
Electronic household appliances, office equipment, audio equipment, consumer equipment, etc.
Rev.0.10 Jul 20, 2007 REJ03B0219-0010
Page 1 of 44
Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
1. Overview
1.1.2
Specifications
Tables 1.1 and 1.2 outlines the Specifications for R8C/2K Group and Tables 1.3 and 1.4 outlines the Specifications for R8C/2L Group Table 1.1
Item CPU
Specifications for R8C/2K Group (1)
Function Central processing unit Specification R8C/Tiny series core * Number of fundamental instructions: 89 * Minimum instruction execution time: 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V) 100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V) 200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V) * Multiplier: 16 bits x 16 bits 32 bits * Multiply-accumulate instruction: 16 bits x 16 bits + 32 bits 32 bits * Operation mode: Single-chip mode (address space: 1 Mbyte) Refer to Table 1.5 Product List for R8C/2K Group. * Power-on reset * Voltage detection 3 * Input-only: 3 pins * CMOS I/O ports: 25, selectable pull-up resistor * High current drive ports: 8 2 circuits: XIN clock oscillation circuit (with on-chip feedback resistor), On-chip oscillator (high-speed, low-speed) (high-speed on-chip oscillator has a frequency adjustment function) * Oscillation stop detection: XIN clock oscillation stop detection function * Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16 * Low power consumption modes: Standard operating mode (high-speed clock, high-speed on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode * External: 4 sources, Internal: 15 sources, Software: 4 sources * Priority levels: 7 levels 15 bits x 1 (with prescaler), reset start selectable 8 bits x 1 (with 8-bit prescaler) Timer mode (period timer), pulse output mode (output level inverted every period), event counter mode, pulse width measurement mode, pulse period measurement mode 8 bits x 1 (with 8-bit prescaler) Timer mode (period timer), programmable waveform generation mode (PWM output), programmable one-shot generation mode, programmable wait oneshot generation mode 16 bits x 1 (with 4 capture/compare registers) Timer mode (input capture function, output compare function), PWM mode (output 3 pins), PWM2 mode (PWM output pin) 16 bits x 2 (with 4 capture/compare registers) Timer mode (input capture function, output compare function), PWM mode (output 6 pins), reset synchronous PWM mode (output three-phase waveforms (6 pins), sawtooth wave modulation), complementary PWM mode (output three-phase waveforms (6 pins), triangular wave modulation), PWM3 mode (PWM output 2 pins with fixed period)
Memory Power Supply Voltage Detection I/O Ports
ROM, RAM Voltage detection circuit Programmable I/O ports Clock generation circuits
Clock
Interrupts Watchdog Timer Timer Timer RA
Timer RB
Timer RC
Timer RD
Rev.0.10 Jul 20, 2007 REJ03B0219-0010
Page 2 of 44
Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
1. Overview
Table 1.2
Specifications for R8C/2K Group (2)
Specification Clock synchronous serial I/O/UART x 2 Hardware LIN: 1 (timer RA, UART0) 10-bit resolution x 9 channels, includes sample and hold function * Programming and erasure voltage: VCC = 2.7 to 5.5 V * Programming and erasure endurance: 100 times * Program security: ROM code protect, ID code check * Debug functions: On-chip debug, on-board flash rewrite function f(XIN) = 20 MHz (VCC = 3.0 to 5.5 V) f(XIN) = 10 MHz (VCC = 2.7 to 5.5 V) f(XIN) = 5 MHz (VCC = 2.2 to 5.5 V) (VCC = 2.7 to 5.5 V for A/D converter only) TBD (VCC = 5.0 V, f(XIN) = 20 MHz) TBD (VCC = 3.0 V, f(XIN) = 10 MHz) TBD (VCC = 3.0 V, wait mode) TBD (VCC = 3.0 V, stop mode) -20 to 85C (N version) -40 to 85C (D version)(1) 32-pin LQFP * Package code: PLQP0032GB-A (previous code: 32P6U-A)
Item Function Serial UART0, UART2 Interface LIN Module A/D Converter Flash Memory
Operating Frequency/Supply Voltage Current consumption
Operating Ambient Temperature Package
NOTE: 1. Specify the D version if D version functions are to be used.
Rev.0.10 Jul 20, 2007 REJ03B0219-0010
Page 3 of 44
Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
1. Overview
Table 1.3
Item CPU
Specifications for R8C/2L Group (1)
Function Central processing unit Specification R8C/Tiny series core * Number of fundamental instructions: 89 * Minimum instruction execution time: 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V) 100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V) 200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V) * Multiplier: 16 bits x 16 bits 32 bits * Multiply-accumulate instruction: 16 bits x 16 bits + 32 bits 32 bits * Operation mode: Single-chip mode (address space: 1 Mbyte) Refer to Table 1.6 Product List for R8C/2L Group. * Power-on reset * Voltage detection 3 * Input-only: 3 pins * CMOS I/O ports: 25, selectable pull-up resistor * High current drive ports: 8 2 circuits: XIN clock oscillation circuit (with on-chip feedback resistor), On-chip oscillator (high-speed, low-speed) (high-speed on-chip oscillator has a frequency adjustment function) * Oscillation stop detection: XIN clock oscillation stop detection function * Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16 * Low power consumption modes: Standard operating mode (high-speed clock, high-speed on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode * External: 4 sources, Internal: 15 sources, Software: 4 sources * Priority levels: 7 levels 15 bits x 1 (with prescaler), reset start selectable 8 bits x 1 (with 8-bit prescaler) Timer mode (period timer), pulse output mode (output level inverted every period), event counter mode, pulse width measurement mode, pulse period measurement mode 8 bits x 1 (with 8-bit prescaler) Timer mode (period timer), programmable waveform generation mode (PWM output), programmable one-shot generation mode, programmable wait oneshot generation mode 16 bits x 1 (with 4 capture/compare registers) Timer mode (input capture function, output compare function), PWM mode (output 3 pins), PWM2 mode (PWM output pin) 16 bits x 2 (with 4 capture/compare registers) Timer mode (input capture function, output compare function), PWM mode (output 6 pins), reset synchronous PWM mode (output three-phase waveforms (6 pins), sawtooth wave modulation), complementary PWM mode (output three-phase waveforms (6 pins), triangular wave modulation), PWM3 mode (PWM output 2 pins with fixed period)
Memory Power Supply Voltage Detection I/O Ports
ROM, RAM Voltage detection circuit Programmable I/O ports Clock generation circuits
Clock
Interrupts Watchdog Timer Timer Timer RA
Timer RB
Timer RC
Timer RD
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Page 4 of 44
Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
1. Overview
Table 1.4
Specifications for R8C/2L Group (2)
Specification Clock synchronous serial I/O/UART x 2 Hardware LIN: 1 (timer RA, UART0) 10-bit resolution x 9 channels, includes sample and hold function * Programming and erasure voltage: VCC = 2.7 to 5.5 V * Programming and erasure endurance: 10,000 times (data flash) 1,000 times (program ROM) * Program security: ROM code protect, ID code check * Debug functions: On-chip debug, on-board flash rewrite function f(XIN) = 20 MHz (VCC = 3.0 to 5.5 V) f(XIN) = 10 MHz (VCC = 2.7 to 5.5 V) f(XIN) = 5 MHz (VCC = 2.2 to 5.5 V) (VCC = 2.7 to 5.5 V for A/D converter only) TBD (VCC = 5.0 V, f(XIN) = 20 MHz) TBD (VCC = 3.0 V, f(XIN) = 10 MHz) TBD (VCC = 3.0 V, wait mode) TBD (VCC = 3.0 V, stop mode) -20 to 85C (N version) -40 to 85C (D version)(1) 32-pin LQFP * Package code: PLQP0032GB-A (previous code: 32P6U-A)
Item Function Serial UART0, UART2 Interface LIN Module A/D Converter Flash Memory
Operating Frequency/Supply Voltage Current consumption
Operating Ambient Temperature Package
NOTE: 1. Specify the D version if D version functions are to be used.
Rev.0.10 Jul 20, 2007 REJ03B0219-0010
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Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
1. Overview
1.2
Product List
Table 1.5 lists Product List for R8C/2K Group, Figure 1.1 shows a Part Number, Memory Size, and Package of R8C/2K Group, Table 1.6 lists Product List for R8C/2L Group, and Figure 1.2 shows a Part Number, Memory Size, and Package of R8C/2L Group. Table 1.5 Product List for R8C/2K Group ROM Capacity 8 Kbytes 16 Kbytes 8 Kbytes 16 Kbytes RAM Capacity 1 Kbyte 1.5 Kbytes 1 Kbyte 1.5 Kbytes Package Type PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A Current of Jul. 2007 Remarks N version D version
Part No. R5F212K2SNFP (D) R5F212K4SNFP (D) R5F212K2SDFP (D) R5F212K4SDFP (D) (D): Under development
Part No.
R 5 F 21 2K 2 S N FP
Package type: FP: PLQP0032GB-A Classification N: Operating ambient temperature -20C to 85C D: Operating ambient temperature -40C to 85C S: Low-voltage version ROM capacity 2: 8 KB 4: 16 KB R8C/2K Group R8C/Tiny Series Memory type F: Flash memory Renesas MCU Renesas semiconductor
Figure 1.1
Part Number, Memory Size, and Package of R8C/2K Group
Rev.0.10 Jul 20, 2007 REJ03B0219-0010
Page 6 of 44
Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
1. Overview
Table 1.6
Product List for R8C/2L Group ROM Capacity Program ROM Data flash 8 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 8 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 RAM Capacity 1 Kbyte 1.5 Kbytes 1 Kbyte 1.5 Kbytes
Current of Jul. 2007 Package Type Remarks
Part No. R5F212L2SNFP (D) R5F212L4SNFP (D) R5F212L2SDFP (D) R5F212L4SDFP (D)
PLQP0032GB-A N version PLQP0032GB-A PLQP0032GB-A D version PLQP0032GB-A
(D): Under development
Part No.
R 5 F 21 2L 2 S N FP
Package type: FP: PLQP0032GB-A Classification N: Operating ambient temperature -20C to 85C D: Operating ambient temperature -40C to 85C S: Low-voltage version ROM capacity 2: 8 KB 4: 16 KB R8C/2L Group R8C/Tiny Series Memory type F: Flash memory Renesas MCU Renesas semiconductor
Figure 1.2
Part Number, Memory Size, and Package of R8C/2L Group
Rev.0.10 Jul 20, 2007 REJ03B0219-0010
Page 7 of 44
Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
1. Overview
1.3
Block Diagram
Figure 1.3 shows a Block Diagram.
5
8
8
3
1
3
I/O ports Peripheral functions
Timers Timer RA (8 bits x 1) Timer RB (8 bits x 1) Timer RC (16 bits x 1) Timer RD (16 bits x 2)
Port P0
Port P1
Port P2
Port P3
Port P4
UART or clock synchronous serial I/O (8 bits x 2)
System clock generation circuit XIN-XOUT High-speed on-chip oscillator Low-speed on-chip oscillator
LIN module
Watchdog timer (15 bits) A/D converter (10 bits x 9 channels)
R8C/Tiny Series CPU core
R0H R1H R2 R3 A0 A1 FB R0L R1L SB USP ISP INTB PC FLG
Memory
ROM(1)
RAM(2)
Multiplier
NOTES: 1. ROM size varies with MCU type. 2. RAM size varies with MCU type.
Figure 1.3
Block Diagram
Rev.0.10 Jul 20, 2007 REJ03B0219-0010
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Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
1. Overview
1.4
Pin Assignment
Figure 1.4 shows Pin Assignment (Top View). Table 1.7 outlines the Pin Name Information by Pin Number.
P1_1/KI1/AN9/TRCIOA/TRCTRG
P1_5/RXD0/(TRAIO)/(INT1)(2) P1_6/CLK0 P1_7/TRAIO/INT1
P1_2/KI2/AN10/TRCIOB P1_3/KI3/AN11/TRBO P1_4/TXD0
24 23 22 21 20 19 18 17
P1_0/KI0/AN8 P3_4/TRCIOC P3_5/TRCIOD P0_5/AN2 P0_3/AN4/CLK2 P0_2/AN5/RXD2 P0_1/AN6/TXD2 P0_0/AN7
P4_5/INT0
16 15 14
25 26 27 28 29 30 31 32 1
R8C/2K Group R8C/2L Group
PLQP0032GB-A (32P6U-A) (top view)
2 3 4 5 6 7 8
13 12 11 10 9
P2_0/TRDIOA0/TRDCLK P2_2/TRDIOC0 P2_1/TRDIOB0 P2_3/TRDIOD0 P2_4/TRDIOA1 P2_5/TRDIOB1 P2_6/TRDIOC1 P2_7/TRDIOD1
VREF/P4_2
NOTES: 1. P4_7 are an input-only port. 2. Can be assigned to the pin in parentheses by a program. 3. Confirm the pin 1 position on the package by referring to the package dimensions.
Figure 1.4
Pin Assignment (Top View)
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P3_3/INT3/TRCCLK
MODE
RESET XOUT/P4_7 (1) VSS/AVSS XIN/P4_6
VCC/AVCC
Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
1. Overview
Table 1.7
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Pin Name Information by Pin Number
Control Pin VREF MODE RESET XOUT VSS/AVSS XIN VCC/AVCC Port P4_2 Interrupt I/O Pin Functions for of Peripheral Modules A/D Converter Timer Serial Interface
P4_7 P4_6 P3_3 P2_7 P2_6 P2_5 P2_4 P2_3 P2_1 P2_2 P2_0 P4_5 P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 P1_1 P1_0 P3_4 P3_5 P0_5 P0_3 P0_2 P0_1 P0_0 INT3 TRCCLK TRDIOD1 TRDIOC1 TRDIOB1 TRDIOA1 TRDIOD0 TRDIOB0 TRDIOC0 TRDIOA0/TRDCLK TRAIO CLK0 (INT1)(1) KI3 KI2 KI1 KI0 TRCIOC TRCIOD CLK2 RXD2 TXD2 AN2 AN4 AN5 AN6 AN7 (TRAIO)(1) TRBO TRCIOB TRCIOA/TRCTRG RXD0 TXD0 AN11 AN10 AN9 AN8
INT0 INT1
NOTE: 1. Can be assigned to the pin in parentheses by a program.
Rev.0.10 Jul 20, 2007 REJ03B0219-0010
Page 10 of 44
Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
1. Overview
1.5
Pin Functions
Table 1.8 lists Pin Functions. Table 1.8
Item Power supply input Analog power supply input Reset input MODE XIN clock input XIN clock output INT interrupt input Key input interrupt Timer RA Timer RB Timer RC
Pin Functions
Pin Name VCC, VSS AVCC, AVSS RESET MODE XIN XOUT INT0, INT1, INT3 KI0 to KI3 TRAIO TRBO TRCCLK TRCTRG TRCIOA, TRCIOB, TRCIOC, TRCIOD I/O Type - - I I I O I I I/O O I I I/O I/O Description Apply 2.2 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin. Power supply for the A/D converter. Connect a capacitor between AVCC and AVSS. Input "L" on this pin resets the MCU. Connect this pin to VCC via a resistor. These pins are provided for XIN clock generation circuit I/O. Connect a ceramic resonator or a crystal oscillator between the XIN and XOUT pins(1). To use an external clock, input it to the XIN pin and leave the XOUT pin open. INT interrupt input pins. INT0 is timer RB, timer RC and timer RD input pins. Key input interrupt input pins Timer RA I/O pin Timer RB output pin External clock input pin External trigger input pin Timer RC I/O pins Timer RD I/O pins
Timer RD
TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1 TRDCLK CLK0, CLK2 RXD0, RXD2 TXD0, TXD2
I I/O I O I I I/O
External clock input pin Transfer clock I/O pins Serial data input pins Serial data output pins Reference voltage input pin to A/D converter Analog input pins to A/D converter CMOS I/O ports. Each port has an I/O select direction register, allowing each pin in the port to be directed for input or output individually. Any port set to input can be set to use a pull-up resistor or not by a program. P2_0 to P2_7 also function as LED drive ports. Input-only ports
Serial interface
Reference voltage input A/D converter I/O port
VREF AN2, AN4 to AN11 P0_0 to P0_3, P0_5, P1_0 to P1_7, P2_0 to P2_7, P3_3 to P3_5, P4_5, P4_2, P4_6, P4_7
Input port
I
I: Input O: Output I/O: Input and output NOTE: 1. Refer to the oscillator manufacturer for oscillation characteristics.
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Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
2. Central Processing Unit (CPU)
2.
Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a register bank. There are two sets of register bank.
b31
b15
b8b7
b0
R2 R3
R0H (high-order of R0) R0L (low-order of R0) R1H (high-order of R1) R1L (low-order of R1) Data registers(1)
R2 R3 A0 A1 FB
b19 b15 b0
Address registers(1) Frame base register(1)
INTBH
INTBL
Interrupt table register
The 4 high order bits of INTB are INTBH and the 16 low order bits of INTB are INTBL.
b19 b0
PC
Program counter
b15
b0
USP ISP SB
b15 b0
User stack pointer Interrupt stack pointer Static base register
FLG
b15 b8 b7 b0
Flag register
IPL
U I OBSZDC
Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved bit Processor interrupt priority level Reserved bit
NOTE: 1. These registers comprise a register bank. There are two register banks.
Figure 2.1
CPU Registers
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Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
2. Central Processing Unit (CPU)
2.1
Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is analogous to R2R0.
2.2
Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the start address of an interrupt vector table.
2.5
Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch between USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1
Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2
Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3
Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4
Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6
Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
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Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
2. Central Processing Unit (CPU)
2.8.7
Interrupt Enable Flag (I)
The I flag enables maskable interrupts. Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0 when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1. The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10
Reserved Bit
If necessary, set to 0. When read, the content is undefined.
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Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
3. Memory
3.
3.1
Memory
R8C/2K Group
Figure 3.1 is a Memory Map of R8C/2K Group. The R8C/2K Group has 1 Mbyte of address space from addresses 00000h to FFFFFh. The internal ROM is allocated lower addresses, beginning with address 0FFFFh. For example, a 16-Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine. The internal RAM is allocated higher addresses beginning with address 00400h. For example, a 1.5-Kbyte internal RAM area is allocated addresses 00400h to 009FFh. The internal RAM is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged. Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use and cannot be accessed by users.
00000h
SFR
(Refer to 4. Special Function Registers (SFRs))
002FFh
00400h
Internal RAM
0XXXh 0FFDCh
Undefined instruction Overflow BRK instruction Address match Single step
Watchdog timer/oscillation stop detection/voltage monitor
0YYYYh
Internal ROM (program ROM)
0FFFFh 0FFFFh
(Reserved) (Reserved) Reset
Expanded area
FFFFFh
NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Part Number R5F212K2SNFP, R5F212K2SDFP R5F212K4SNFP, R5F212K4SDFP Internal ROM Size 8 Kbytes 16 Kbytes Address 0YYYYh 0E000h 0C000h Size 1 Kbyte 1.5 Kbytes Internal RAM Address 0XXXXh 007FFh 009FFh
Figure 3.1
Memory Map of R8C/2K Group
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Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
3. Memory
3.2
R8C/2L Group
Figure 3.2 is a Memory Map of R8C/2L Group. The R8C/2L Group has 1 Mbyte of address space from addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a 16-Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine. The internal ROM (data flash) is allocated addresses 02400h to 02BFFh. The internal RAM area is allocated higher addresses, beginning with address 00400h. For example, a 1.5-Kbyte internal RAM is allocated addresses 00400h to 009FFh. The internal RAM is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged. Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use and cannot be accessed by users.
00000h
SFR
(Refer to 4. Special Function Registers (SFRs))
002FFh
00400h
Internal RAM
0XXXXh 02400h
Internal ROM (data flash)(1)
02BFFh
0FFDCh
Undefined instruction Overflow BRK instruction Address match Single step
Watchdog timer/oscillation stop detection/voltage monitor
0YYYYh
Internal ROM (program ROM)
0FFFFh 0FFFFh
(Reserved) (Reserved) Reset
Expanded area
FFFFFh
NOTES: 1. Data flash block A (1 Kbyte) and B (1 Kbyte) are shown. 2. The blank regions are reserved. Do not access locations in these regions. Part Number R5F212L2SNFP, R5F212L2SDFP R5F212L4SNFP, R5F212L4SDFP Internal ROM Size 8 Kbytes 16 Kbytes Address 0YYYYh 0E000h 0C000h Size 1 Kbyte 1.5 Kbytes Address 0XXXXh 007FFh 009FFh
Figure 3.2
Memory Map of R8C/2L Group
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Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
4. Special Function Registers (SFRs)
4.
Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.7 list the special function registers. Table 4.1
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect this register. 3. The LVD0ON bit in the OFS register is set to 1 and hardware reset. 4. Power-on reset, voltage monitor 0 reset, or the LVD0ON bit in the OFS register is set to 0 and hardware reset. 5. Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect b2 and b3. 6. The CSPROINI bit in the OFS register is set to 0.
SFR Information (1)(1)
Register Symbol After reset
Processor Mode Register 0 Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1
PM0 PM1 CM0 CM1
00h 00h 01101000b 00100000b
Protect Register Oscillation Stop Detection Register Watchdog Timer Reset Register Watchdog Timer Start Register Watchdog Timer Control Register Address Match Interrupt Register 0
PRCR OCD WDTR WDTS WDC RMAD0
00h 00000100b XXh XXh 00X11111b 00h 00h 00h 00h 00h 00h 00h
Address Match Interrupt Enable Register Address Match Interrupt Register 1
AIER RMAD1
Count Source Protection Mode Register
CSPR
00h 10000000b(6)
High-Speed On-Chip Oscillator Control Register 0 High-Speed On-Chip Oscillator Control Register 1 High-Speed On-Chip Oscillator Control Register 2
FRA0 FRA1 FRA2
00h When shipping 00h
High-Speed On-Chip Oscillator Control Register 6
FRA6
When Shipping
Voltage Detection Register 1(2) Voltage Detection Register 2(2)
VCA1 VCA2
00001000b 00h(3) 00100000b(4)
Voltage Monitor 1 Circuit Control Register(5) Voltage Monitor 2 Circuit Control Register(5) Voltage Monitor 0 Circuit Control Register(2)
VW1C VW2C VW0C
00001000b 00h 0000X000b(3) 0100X001b(4)
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Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
4. Special Function Registers (SFRs)
Table 4.2
Address 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh
SFR Information (2)(1)
Register Symbol After reset
Timer RC Interrupt Control Register Timer RD0 Interrupt Control Register Timer RD1 Interrupt Control Register UART2 Transmit Interrupt Control Register UART2 Receive Interrupt Control Register Key Input Interrupt Control Register A/D Conversion Interrupt Control Register
TRCIC TRD0IC TRD1IC S2TIC S2RIC KUPIC ADIC
XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b
UART0 Transmit Interrupt Control Register UART0 Receive Interrupt Control Register
S0TIC S0RIC
XXXXX000b XXXXX000b
Timer RA Interrupt Control Register Timer RB Interrupt Control Register INT1 Interrupt Control Register INT3 Interrupt Control Register
TRAIC TRBIC INT1IC INT3IC
XXXXX000b XXXXX000b XX00X000b XX00X000b
INT0 Interrupt Control Register
INT0IC
XX00X000b
X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions.
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Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
4. Special Function Registers (SFRs)
Table 4.3
Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh
SFR Information (3)(1)
Register Symbol After reset
UART0 Transmit/Receive Mode Register UART0 Bit Rate Register UART0 Transmit Buffer Register UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register
U0MR U0BRG U0TB U0C0 U0C1 U0RB
00h XXh XXh XXh 00001000b 00000010b XXh XXh
X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions.
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Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
4. Special Function Registers (SFRs)
Table 4.4
Address 00C0h 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h 00D5h 00D6h 00D7h 00D8h 00D9h 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh 00E0h 00E1h 00E2h 00E3h 00E4h 00E5h 00E6h 00E7h 00E8h 00E9h 00EAh 00EBh 00ECh 00EDh 00EEh 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh
SFR Information (4)(1)
Register A/D Register AD Symbol XXh XXh After reset
A/D Control Register 2 A/D Control Register 0 A/D Control Register 1
ADCON2 ADCON0 ADCON1
00001000b 00000011b 00h
Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P2 Register Port P3 Register Port P2 Direction Register Port P3 Direction Register Port P4 Register Port P4 Direction Register
P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 PD4
XXh XXh 00h 00h XXh XXh 00h 00h XXh 00h
Port P2 Drive Capacity Control Register
P2DRR
00h
External Input Enable Register INT Input Filter Select Register Key Input Enable Register Pull-Up Control Register 0 Pull-Up Control Register 1
INTEN INTF KIEN PUR0 PUR1
00h 00h 00h 00h XX000000b
X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions.
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Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
4. Special Function Registers (SFRs)
Table 4.5
Address 0100h 0101h 0102h 0103h 0104h 0105h 0106h 0107h 0108h 0109h 010Ah 010Bh 010Ch 010Dh 010Eh 010Fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h 0119h 011Ah 011Bh 011Ch 011Dh 011Eh 011Fh 0120h 0121h 0122h 0123h 0124h 0125h 0126h 0127h 0128h 0129h 012Ah 012Bh 012Ch 012Dh 012Eh 012Fh 0130h 0131h 0132h 0133h 0134h 0135h 0136h 0137h 0138h 0139h 013Ah 013Bh 013Ch 013Dh 013Eh 013Fh NOTE: 1.
SFR Information (5)(1)
Register Timer RA Control Register Timer RA I/O Control Register Timer RA Mode Register Timer RA Prescaler Register Timer RA Register LIN Control Register 2 LIN Control Register LIN Status Register Timer RB Control Register Timer RB One-Shot Control Register Timer RB I/O Control Register Timer RB Mode Register Timer RB Prescaler Register Timer RB Secondary Register Timer RB Primary Register Symbol TRACR TRAIOC TRAMR TRAPRE TRA LINCR2 LINCR LINST TRBCR TRBOCR TRBIOC TRBMR TRBPRE TRBSC TRBPR After reset 00h 00h 00h FFh FFh 00h 00h 00h 00h 00h 00h 00h FFh FFh FFh
Timer RC Mode Register Timer RC Control Register 1 Timer RC Interrupt Enable Register Timer RC Status Register Timer RC I/O Control Register 0 Timer RC I/O Control Register 1 Timer RC Counter Timer RC General Register A Timer RC General Register B Timer RC General Register C Timer RC General Register D Timer RC Control Register 2 Timer RC Digital Filter Function Select Register Timer RC Output Master Enable Register
TRCMR TRCCR1 TRCIER TRCSR TRCIOR0 TRCIOR1 TRC TRCGRA TRCGRB TRCGRC TRCGRD TRCCR2 TRCDF TRCOER
01001000b 00h 01110000b 01110000b 10001000b 10001000b 00h 00h FFh FFh FFh FFh FFh FFh FFh FFh 00011111b 00h 01111111b
Timer RD Start Register Timer RD Mode Register Timer RD PWM Mode Register Timer RD Function Control Register Timer RD Output Master Enable Register 1 Timer RD Output Master Enable Register 2 Timer RD Output Control Register Timer RD Digital Filter Function Select Register 0 Timer RD Digital Filter Function Select Register 1
TRDSTR TRDMR TRDPMR TRDFCR TRDOER1 TRDOER2 TRDOCR TRDDF0 TRDDF1
11111100b 00001110b 10001000b 10000000b FFh 01111111b 00h 00h 00h
The blank regions are reserved. Do not access locations in these regions
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Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
4. Special Function Registers (SFRs)
Table 4.6
Address 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014Ah 014Bh 014Ch 014Dh 014Eh 014Fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015Ah 015Bh 015Ch 015Dh 015Eh 015Fh 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016Ah 016Bh 016Ch 016Dh 016Eh 016Fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017Ah 017Bh 017Ch 017Dh 017Eh 017Fh
SFR Information (6)(1)
Register Timer RD Control Register 0 Timer RD I/O Control Register A0 Timer RD I/O Control Register C0 Timer RD Status Register 0 Timer RD Interrupt Enable Register 0 Timer RD PWM Mode Output Level Control Register 0 Timer RD Counter 0 Timer RD General Register A0 Timer RD General Register B0 Timer RD General Register C0 Timer RD General Register D0 Timer RD Control Register 1 Timer RD I/O Control Register A1 Timer RD I/O Control Register C1 Timer RD Status Register 1 Timer RD Interrupt Enable Register 1 Timer RD PWM Mode Output Level Control Register 1 Timer RD Counter 1 Timer RD General Register A1 Timer RD General Register B1 Timer RD General Register C1 Timer RD General Register D1 UART2 Transmit/Receive Mode Register UART2 Bit Rate Register UART2 Transmit Buffer Register UART2 Transmit/Receive Control Register 0 UART2 Transmit/Receive Control Register 1 UART2 Receive Buffer Register Symbol TRDCR0 TRDIORA0 TRDIORC0 TRDSR0 TRDIER0 TRDPOCR0 TRD0 TRDGRA0 TRDGRB0 TRDGRC0 TRDGRD0 TRDCR1 TRDIORA1 TRDIORC1 TRDSR1 TRDIER1 TRDPOCR1 TRD1 TRDGRA1 TRDGRB1 TRDGRC1 TRDGRD1 U2MR U2BRG U2TB U2C0 U2C1 U2RB After reset 00h 10001000b 10001000b 11000000b 11100000b 11111000b 00h 00h FFh FFh FFh FFh FFh FFh FFh FFh 00h 10001000b 10001000b 11000000b 11100000b 11111000b 00h 00h FFh FFh FFh FFh FFh FFh FFh FFh 00h XXh XXh XXh 00001000b 00000010b XXh XXh
X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions.
Rev.0.10 Jul 20, 2007 REJ03B0219-0010
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Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
4. Special Function Registers (SFRs)
Table 4.7
Address 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh 01AEh 01AFh 01B0h 01B1h 01B2h 01B3h 01B4h 01B5h 01B6h 01B7h 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh 01BFh FFFFh
SFR Information (7)(1)
Register Symbol After reset
Flash Memory Control Register 4 Flash Memory Control Register 1 Flash Memory Control Register 0
FMR4 FMR1 FMR0
01000000b 1000000Xb 00000001b
Option Function Select Register
OFS
(Note 2)
X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions. 2. The OFS register cannot be changed by a program. Use a flash programmer to write to it.
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Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
5. Electrical Characteristics
5.
Electrical Characteristics
Table 5.1
Symbol VCC/AVCC VI VO Pd Topr Tstg Supply voltage Input voltage Output voltage Power dissipation Operating ambient temperature Storage temperature Topr = 25C
Absolute Maximum Ratings
Parameter Condition Rated Value -0.3 to 6.5 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 500 -20 to 85 (N version) / -40 to 85 (D version) -65 to 150 Unit V V V mW C C
Table 5.2
Symbol VCC AVCC VSS/AVSS VIH VIL IOH(sum) IOH(sum) IOH(peak) IOH(avg) IOL(sum) IOL(sum)
Recommended Operating Conditions
Parameter Supply voltage Supply voltage Supply voltage Input "H" voltage Input "L" voltage Peak sum output "H" current Average sum output "H" current Peak output "H" current Average output "H" current Peak sum output "L" currents Average sum output "L" currents Peak output "L" currents Conditions Min. 2.2 2.7 - 0.8 VCC 0 - - - - - - - - Standard Typ. - - 0 - - - - - - - - - - Max. 5.5 5.5 - VCC 0.2 VCC -160 -80 -10 -40 -5 -20 160 80 Unit V V V V mA mA mA mA mA mA mA mA
Sum of all pins IOH(peak) Sum of all pins IOH(avg) Except P2_0 to P2_7 P2_0 to P2_7 Except P2_0 to P2_7 P2_0 to P2_7 Sum of all pins IOL(peak) Sum of all pins IOL(avg)
IOL(peak) IOL(avg) f(XIN)
Except P2_0 to P2_7 P2_0 to P2_7 Average output Except P2_0 to P2_7 "L" current P2_0 to P2_7 XIN clock input oscillation frequency
-
System clock
OCD2 = 0 XlN clock selected OCD2 = 1 On-chip oscillator clock selected
3.0 V VCC 5.5 V 2.7 V VCC < 3.0 V 2.2 V VCC < 2.7 V 3.0 V VCC 5.5 V 2.7 V VCC < 3.0 V 2.2 V VCC < 2.7 V FRA01 = 0 Low-speed on-chip oscillator clock selected FRA01 = 1 High-speed on-chip oscillator clock selected 3.0 V VCC 5.5 V FRA01 = 1 High-speed on-chip oscillator clock selected 2.7 V VCC 5.5 V FRA01 = 1 High-speed on-chip oscillator clock selected 2.2 V VCC 5.5 V
- - - - 0 0 0 0 0 0 - -
- - - - - - - - - - 125 -
10 40 5 20 20 10 5 20 10 5 -
mA mA mA mA MHz MHz MHz MHz MHz MHz kHz
20
MHz
-
-
10
MHz
-
-
5
MHz
NOTES: 1. VCC = 2.2 to 5.5 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. The typical values when average output current is 100 ms.
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Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
5. Electrical Characteristics
Table 5.3
Symbol - -
A/D Converter Characteristics
Parameter Resolution Absolute accuracy 10-bit mode 8-bit mode 10-bit mode 8-bit mode Vref = AVCC AD = 10 MHz, Vref = AVCC = 5.0 V AD = 10 MHz, Vref = AVCC = 5.0 V AD = 10 MHz, Vref = AVCC = 3.3 V AD = 10 MHz, Vref = AVCC = 3.3 V Vref = AVCC AD = 10 MHz, Vref = AVCC = 5.0 V AD = 10 MHz, Vref = AVCC = 5.0 V 8-bit mode Conditions Standard Min. - - - - - 10 3.3 2.8 2.2 0 Vref = AVCC = 2.7 to 5.5 V Vref = AVCC = 2.7 to 5.5 V 0.25 1 Without sample and hold With sample and hold Typ. - - - - - - - - - - - - Max. 10 3 2 5 2 40 - - AVCC AVCC 10 10 Unit Bits LSB LSB LSB LSB k s s V V MHz MHz
Rladder tconv Vref VIA -
Resistor ladder Conversion time 10-bit mode Reference voltage Analog input voltage(2) A/D operating clock frequency
NOTES: 1. AVCC = 2.7 to 5.5 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in 8-bit mode.
P0 P1 P2 P3 P4 30pF
Figure 5.1
Ports P0 to P4 Timing Measurement Circuit
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Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
5. Electrical Characteristics
Table 5.4
Symbol - - - td(SR-SUS) - - - - - - -
Flash Memory (Program ROM) Electrical Characteristics
Parameter Program/erase endurance(2) Byte program time Block erase time Time delay from suspend request until suspend Interval from erase start/restart until following suspend request Interval from program start/restart until following suspend request Time from suspend until program/erase restart Program, erase voltage Read voltage Program, erase temperature Data hold time(7) Ambient temperature = 55C Conditions R8C/2K Group R8C/2L Group Standard Min. 100(3) 1,000(3) - - - 650 0 - 2.7 2.2 0 20 Typ. - - 50 0.4 - - - - - - - - Max. - - 400 9 97+CPU clock x 6 cycles - - 3+CPU clock x 4 cycles 5.5 5.5 60 - Unit times times s s s s ns s V V C year
NOTES: 1. VCC = 2.7 to 5.5 V at Topr = 0 to 60C, unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 7. The data hold time includes time that the power supply is off or the clock is not supplied.
Rev.0.10 Jul 20, 2007 REJ03B0219-0010
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Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
5. Electrical Characteristics
Table 5.5
Symbol - - - - - td(SR-SUS) - - - - - - -
Flash Memory (Data flash Block A, Block B) Electrical Characteristics(4)
Parameter Program/erase endurance(2) Byte program time (program/erase endurance 1,000 times) Byte program time (program/erase endurance > 1,000 times) Block erase time (program/erase endurance 1,000 times) Block erase time (program/erase endurance > 1,000 times) Time delay from suspend request until suspend Interval from erase start/restart until following suspend request Interval from program start/restart until following suspend request Time from suspend until program/erase restart Program, erase voltage Read voltage Program, erase temperature Data hold time(9) Ambient temperature = 55 C Conditions Standard Min. 10,000(3) - - - - - 650 0 - 2.7 2.2 -20(8) 20 Typ. - 50 65 0.2 0.3 - - - - - - - - Max. - 400 - 9 - 97+CPU clock x 6 cycles - - 3+CPU clock x 4 cycles 5.5 5.5 85 - Unit times s s s s s s ns s V V C year
NOTES: 1. VCC = 2.7 to 5.5 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 4. Standard of block A and block B when program and erase endurance exceeds 1,000 times. Byte program time to 1,000 times is the same as that in program ROM. 5. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 7. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 8. -40C for D version. 9. The data hold time includes time that the power supply is off or the clock is not supplied.
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Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
5. Electrical Characteristics
Suspend request (maskable interrupt request)
FMR46
Fixed time Clock-dependent time Access restart
td(SR-SUS)
Figure 5.2
Time delay until Suspend
Table 5.6
Symbol Vdet0 - td(E-A) Vccmin
Voltage Detection 0 Circuit Electrical Characteristics
Parameter Voltage detection level Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts(2) MCU operating voltage minimum value VCA25 = 1, VCC = 5.0 V Condition Standard Min. 2.2 - - 2.2 Typ. 2.3 0.9 - - Max. 2.4 - 300 - Unit V A s V
NOTES: 1. The measurement condition is VCC = 2.2 V to 5.5 V and Topr = -20 to 85C (N version) / -40 to 85C (D version). 2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2 register to 0.
Table 5.7
Symbol Vdet1 - - td(E-A)
Voltage Detection 1 Circuit Electrical Characteristics
Parameter Voltage detection level(4) Voltage monitor 1 interrupt request generation time(2) VCA26 = 1, VCC = 5.0 V Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts(3) Condition Standard Min. 2.70 - - - Typ. 2.85 40 0.6 - Max. 3.00 - - 100 Unit V s A s
NOTES: 1. The measurement condition is VCC = 2.2 V to 5.5 V and Topr = -20 to 85C (N version) / -40 to 85C (D version). 2. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1. 3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2 register to 0. 4. This parameter shows the voltage detection level when the power supply drops. The voltage detection level when the power supply rises is higher than the voltage detection level when the power supply drops by approximately 0.1 V.
Table 5.8
Symbol Vdet2 - - td(E-A)
Voltage Detection 2 Circuit Electrical Characteristics
Parameter Voltage detection level Voltage monitor 2 interrupt request generation time(2) Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts(3) VCA27 = 1, VCC = 5.0 V Condition Standard Min. 3.3 - - - Typ. 3.6 40 0.6 - Max. 3.9 - - 100 Unit V s A s
NOTES: 1. The measurement condition is VCC = 2.2 V to 5.5 V and Topr = -20 to 85C (N version) / -40 to 85C (D version). 2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2. 3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2 register to 0.
Rev.0.10 Jul 20, 2007 REJ03B0219-0010
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Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
5. Electrical Characteristics
Table 5.9
Symbol Vpor1 Vpor2 trth
Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical Characteristics(3)
Parameter Power-on reset valid voltage(4) Power-on reset or voltage monitor 0 reset valid voltage External power VCC rise gradient(2) Condition Standard Min. - 0 20 Typ. - - - Max. 0.1 Vdet0 - Unit V V mV/msec
NOTES: 1. The measurement condition is Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. This condition (external power VCC rise gradient) does not apply if VCC 1.0 V. 3. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register to 0, the VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to 1. 4. tw(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on reset. When turning on the power for the first time, maintain tw(por1) for 30 s or more if -20C Topr 85C, maintain tw(por1) for 3,000 s or more if -40C Topr < -20C.
Vdet0(3) 2.2V External Power VCC Vpor1 tw(por1) Sampling time(1, 2) trth Vpor2 trth
Vdet0(3)
Internal reset signal ("L" valid) 1 x 32 fOCO-S 1 x 32 fOCO-S
NOTES: 1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage range (2.2 V or above) during the sampling time. 2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit for details. 3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection Circuit for details.
Figure 5.3
Reset Circuit Electrical Characteristics
Rev.0.10 Jul 20, 2007 REJ03B0219-0010
Page 29 of 44
Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
5. Electrical Characteristics
Table 5.10
Symbol fOCO40M
High-speed On-Chip Oscillator Circuit Electrical Characteristics
Parameter High-speed on-chip oscillator frequency temperature * supply voltage dependence Condition VCC = 2.7 V to 5.5 V -20C Topr 85C(2) VCC = 2.7 V to 5.5 V -40C Topr 85C(2) VCC = 2.2 V to 5.5 V -20C Topr 85C(3) VCC = 2.2 V to 5.5 V -40C Topr 85C(3) Standard Min. 39.2 39.0 35.2 34.0 08h Adjust FRA1 register (value after reset) to -1 VCC = 5.0 V, Topr = 25C VCC = 5.0 V, Topr = 25C - - - Typ. 40 40 40 40 - +0.3 10 550 Max. 40.8 41.0 44.8 46.0 F7h - 100 - Unit MHz MHz MHz MHz - MHz s A
- - - -
Value in FRA1 register after reset Oscillation frequency adjustment unit of highspeed on-chip oscillator Oscillation stability time Self power consumption at oscillation
NOTES: 1. VCC = 2.2 to 5.5 V, Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. These standard values show when the FRA1 register value after reset is assumed. 3. These standard values show when the corrected value of the FRA6 register is written to the FRA1 register.
Table 5.11
Symbol fOCO-S - -
Low-speed On-Chip Oscillator Circuit Electrical Characteristics
Parameter Low-speed on-chip oscillator frequency Oscillation stability time Self power consumption at oscillation VCC = 5.0 V, Topr = 25C Condition Standard Min. 30 - - Typ. 125 10 15 Max. 250 100 - Unit kHz s A
NOTE: 1. VCC = 2.2 to 5.5 V, Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified.
Table 5.12
Symbol td(P-R) td(R-S)
Power Supply Circuit Timing Characteristics
Parameter Time for internal power supply stabilization during power-on(2) STOP exit time(3) Condition Standard Min. 1 - Typ. - - Max. 2000 150 Unit s s
NOTES: 1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = 25C. 2. Waiting time until the internal power supply generation circuit stabilizes during power-on. 3. Time until system clock supply starts after the interrupt is acknowledged to exit stop mode.
Rev.0.10 Jul 20, 2007 REJ03B0219-0010
Page 30 of 44
Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
5. Electrical Characteristics
Table 5.13
Symbol VOH
Electrical Characteristics (1) [VCC = 5 V]
Parameter Condition IOH = -5 mA IOH = -200 A Drive capacity HIGH IOH = -20 mA Drive capacity LOW XOUT Drive capacity LOW IOH = -5 mA IOH = -500 A Drive capacity HIGH IOH = -1 mA IOL = 5 mA IOL = 200 A Drive capacity HIGH IOL = 20 mA Drive capacity LOW XOUT Drive capacity LOW IOL = 5 mA IOL = 500 A Drive capacity HIGH IOL = 1 mA Standard Min. VCC - 2.0 VCC - 0.5 VCC - 2.0 VCC - 2.0 VCC - 2.0 VCC - 2.0 - - - - - - 0.1 Typ. - - - - - - - - - - - - 0.5 Max. VCC VCC VCC VCC VCC VCC 2.0 0.45 2.0 2.0 2.0 2.0 - Unit V V V V V V V V V V V V V
Output "H" voltage
Except P2_0 to P2_7, XOUT P2_0 to P2_7
VOL
Output "L" voltage Except P2_0 to P2_7, XOUT P2_0 to P2_7
VT+-VT-
Hysteresis
INT0, INT1, INT3, KI0, KI1, KI2, KI3, TRAIO, RXD0, RXD2, CLK0, CLK2 RESET VI = 5 V, VCC = 5 V VI = 0 V, VCC = 5 V VI = 0 V, VCC = 5 V XIN During stop mode
0.1 - - 30 - 1.8
1.0 - - 50 1.0 -
- 5.0 -5.0 167 - -
V A A k M V
IIH IIL RfXIN VRAM
Input "H" current Input "L" current Feedback resistance RAM hold voltage
RPULLUP Pull-up resistance
NOTE: 1. VCC = 4.2 to 5.5 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), f(XIN) = 20 MHz, unless otherwise specified.
Rev.0.10 Jul 20, 2007 REJ03B0219-0010
Page 31 of 44
Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
5. Electrical Characteristics
Table 5.14
Electrical Characteristics (2) [Vcc = 5 V] (Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified.)
Parameter Condition
XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8
Symbol ICC
Standard Min. - Typ. TBD Max. TBD
Unit mA
Power supply High-speed current clock mode (VCC = 3.3 to 5.5 V) Single-chip mode, output pins are open, other pins are VSS
-
TBD
TBD
mA
-
TBD
-
mA
-
TBD
-
mA
-
TBD
-
mA
-
TBD
-
mA
High-speed on-chip oscillator mode
XIN clock off High-speed on-chip oscillator on fOCO = 20 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO = 20 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8
-
TBD
TBD
mA
-
TBD
-
mA
-
TBD
TBD
mA
-
TBD
-
mA
Low-speed on-chip oscillator mode
XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR47 = 1
-
TBD
TBD
A
Rev.0.10 Jul 20, 2007 REJ03B0219-0010
Page 32 of 44
Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
5. Electrical Characteristics
Table 5.15
Electrical Characteristics (3) [Vcc = 5 V] (Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified.)
Parameter Condition
XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off, Topr = 25C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 85C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0
Symbol ICC
Standard Min. - Typ. TBD Max. TBD
Unit A
Power supply Wait mode current (VCC = 3.3 to 5.5 V) Single-chip mode, output pins are open, other pins are VSS
-
TBD
TBD
A
Stop mode
-
TBD
TBD
A
-
TBD
-
A
Rev.0.10 Jul 20, 2007 REJ03B0219-0010
Page 33 of 44
Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group Timing Requirements (Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25C) [VCC = 5 V] Table 5.16
Symbol tc(XIN) tWH(XIN) tWL(XIN) XIN input cycle time XIN input "H" width XIN input "L" width
5. Electrical Characteristics
XIN Input
Parameter Standard Min. 50 25 25 Max. - - - Unit ns ns ns
tC(XIN) tWH(XIN)
VCC = 5 V
XIN input
tWL(XIN)
Figure 5.4
XIN Input Timing Diagram when VCC = 5 V
Table 5.17
Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO)
TRAIO Input
Parameter TRAIO input cycle time TRAIO input "H" width TRAIO input "L" width Standard Min. 100 40 40 Max. - - - Unit ns ns ns
tC(TRAIO) tWH(TRAIO)
VCC = 5 V
TRAIO input
tWL(TRAIO)
Figure 5.5
TRAIO Input Timing Diagram when VCC = 5 V
Rev.0.10 Jul 20, 2007 REJ03B0219-0010
Page 34 of 44
Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
5. Electrical Characteristics
Table 5.18
Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0, 2
Serial Interface
Parameter CLKi input cycle time CLKi input "H" width CLKi input "L" width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Standard Min. 200 100 100 - 0 50 90 Max. - - - 50 - - - Unit ns ns ns ns ns ns ns
tC(CK) tW(CKH)
VCC = 5 V
CLKi
tW(CKL) th(C-Q)
TXDi
td(C-Q) tsu(D-C) th(C-D)
RXDi i = 0, 2
Figure 5.6
Serial Interface Timing Diagram when VCC = 5 V
Table 5.19
Symbol tW(INH) tW(INL)
External Interrupt INTi (i = 0, 1, 3) Input
Parameter INTi input "H" width INTi input "L" width Standard Min. 250(1) 250(2) Max. - - Unit ns ns
NOTES: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater.
VCC = 5 V
tW(INL)
INTi input
tW(INH)
i = 0, 1, 3
Figure 5.7
External Interrupt INTi Input Timing Diagram when VCC = 5 V
Rev.0.10 Jul 20, 2007 REJ03B0219-0010
Page 35 of 44
Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
5. Electrical Characteristics
Table 5.20
Symbol VOH
Electrical Characteristics (3) [VCC = 3 V]
Parameter Condition IOH = -1 mA Drive capacity HIGH Drive capacity LOW XOUT Drive capacity HIGH Drive capacity LOW IOH = -5 mA IOH = -1 mA IOH = -0.1 mA IOH = -50 A Standard Min. VCC - 0.5 VCC - 0.5 VCC - 0.5 VCC - 0.5 VCC - 0.5 - IOL = 5 mA IOL = 1 mA IOL = 0.1 mA IOL = 50 A - - - - 0.1 Typ. - - - - - - - - - - 0.3 Max. VCC VCC VCC VCC VCC 0.5 0.5 0.5 0.5 0.5 - Unit V V V V V V V V V V V
Output "H" voltage
Except P2_0 to P2_7, XOUT P2_0 to P2_7
VOL
Output "L" voltage
Except P2_0 to P2_7, XOUT P2_0 to P2_7
IOL = 1 mA Drive capacity HIGH Drive capacity LOW
XOUT
Drive capacity HIGH Drive capacity LOW
VT+-VT-
Hysteresis
INT0, INT1, INT3, KI0, KI1, KI2, KI3, TRAIO, RXD0, RXD2, CLK0, CLK2 RESET VI = 3 V, VCC = 3 V VI = 0 V, VCC = 3 V VI = 0 V, VCC = 3 V XIN During stop mode
0.1 - - 66 - 1.8
0.4 - - 160 3.0 -
- 4.0 -4.0 500 - -
V A A k M V
IIH IIL RfXIN VRAM
Input "H" current Input "L" current Feedback resistance RAM hold voltage
RPULLUP Pull-up resistance
NOTE: 1. VCC =2.7 to 3.3 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), f(XIN) = 10 MHz, unless otherwise specified.
Rev.0.10 Jul 20, 2007 REJ03B0219-0010
Page 36 of 44
Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
5. Electrical Characteristics
Table 5.21
Electrical Characteristics (4) [Vcc = 3 V] (Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified.)
Parameter Condition XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR47 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 Stop mode XIN clock off, Topr = 25C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 85C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 Standard Min. - Typ. TBD Max. - Unit mA
Symbol ICC
Power supply current High-speed (VCC = 2.7 to 3.3 V) clock mode Single-chip mode, output pins are open, other pins are VSS
-
TBD
-
mA
High-speed on-chip oscillator mode
-
TBD
TBD
mA
-
TBD
-
mA
Low-speed on-chip oscillator mode Wait mode
-
TBD
TBD
A
-
TBD
TBD
A
-
TBD
TBD
A
-
TBD
TBD
A
-
TBD
-
A
Rev.0.10 Jul 20, 2007 REJ03B0219-0010
Page 37 of 44
Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
Timing requirements (Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = 25C) [VCC = 3 V] Table 5.22
Symbol tc(XIN) tWH(XIN) tWL(XIN) XIN input cycle time XIN input "H" width XIN input "L" width
5. Electrical Characteristics
XIN Input
Parameter Standard Min. 100 40 40 Max. - - - Unit ns ns ns
tC(XIN) tWH(XIN)
VCC = 3 V
XIN input
tWL(XIN)
Figure 5.8
XIN Input Timing Diagram when VCC = 3 V
Table 5.23
Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO)
TRAIO Input
Parameter TRAIO input cycle time TRAIO input "H" width TRAIO input "L" width Standard Min. 300 120 120 Max. - - - Unit ns ns ns
tC(TRAIO) tWH(TRAIO)
VCC = 3 V
TRAIO input
tWL(TRAIO)
Figure 5.9
TRAIO Input Timing Diagram when VCC = 3 V
Rev.0.10 Jul 20, 2007 REJ03B0219-0010
Page 38 of 44
Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
5. Electrical Characteristics
Table 5.24
Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0, 2
Serial Interface
Parameter CLKi input cycle time CLKi input "H" width CLKi Input "L" width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Standard Min. 300 150 150 - 0 70 90 Max. - - - 80 - - - Unit ns ns ns ns ns ns ns
tC(CK) tW(CKH)
VCC = 3 V
CLKi
tW(CKL) th(C-Q)
TXDi
td(C-Q) tsu(D-C) th(C-D)
RXDi i = 0, 2
Figure 5.10
Serial Interface Timing Diagram when VCC = 3 V
Table 5.25
Symbol tW(INH) tW(INL)
External Interrupt INTi (i = 0, 1, 3) Input
Parameter INTi input "H" width INTi input "L" width Standard Min. 380(1) 380(2) Max. - - Unit ns ns
NOTES: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater.
VCC = 3 V
tW(INL)
INTi input
tW(INH)
i = 0, 1, 3
Figure 5.11
External Interrupt INTi Input Timing Diagram when VCC = 3 V
Rev.0.10 Jul 20, 2007 REJ03B0219-0010
Page 39 of 44
Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
5. Electrical Characteristics
Table 5.26
Symbol VOH
Electrical Characteristics (5) [VCC = 2.2 V]
Parameter Condition IOH = -1 mA Drive capacity HIGH Drive capacity LOW XOUT Drive capacity HIGH Drive capacity LOW IOH = -2 mA IOH = -1 mA Standard Min. VCC - 0.5 VCC - 0.5 VCC - 0.5 Typ. - - - - - - - - - - 0.3 Max. VCC VCC VCC VCC VCC 0.5 0.5 0.5 0.5 0.5 - Unit V V V V V V V V V V V
Output "H" voltage
Except P2_0 to P2_7, XOUT P2_0 to P2_7
IOH = -0.1 mA VCC - 0.5 IOH = -50 A VCC - 0.5 - IOL = 2 mA IOL = 1 mA IOL = 0.1 mA IOL = 50 A - - - - 0.05
VOL
Output "L" voltage
Except P2_0 to P2_7, XOUT P2_0 to P2_7
IOL = 1 mA Drive capacity HIGH Drive capacity LOW
XOUT
Drive capacity HIGH Drive capacity LOW
VT+-VT-
Hysteresis
INT0, INT1, INT3, KI0, KI1, KI2, KI3, TRAIO, RXD0, RXD2, CLK0, CLK2 RESET VI = 2.2 V VI = 0 V VI = 0 V XIN During stop mode
0.05 - - 100 - 1.8
0.15 - - 200 5 -
- 4.0 -4.0 600 - -
V A A k M V
IIH IIL RfXIN VRAM
Input "H" current Input "L" current Feedback resistance RAM hold voltage
RPULLUP Pull-up resistance
NOTE: 1. VCC = 2.2 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), f(XIN) = 5 MHz, unless otherwise specified.
Rev.0.10 Jul 20, 2007 REJ03B0219-0010
Page 40 of 44
Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
5. Electrical Characteristics
Table 5.27
Electrical Characteristics (6) [Vcc = 2.2 V] (Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified.)
Parameter Condition XIN = 5 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 5 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO = 5 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO = 5 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR47 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 Stop mode XIN clock off, Topr = 25C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 85C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 Standard Min. - Typ. TBD Max. - Unit mA
Symbol ICC
Power supply current High-speed (VCC = 2.2 to 2.7 V) clock mode Single-chip mode, output pins are open, other pins are VSS
-
TBD
-
mA
High-speed on-chip oscillator mode
-
TBD
-
mA
-
TBD
-
mA
Low-speed on-chip oscillator mode Wait mode
-
TBD
TBD
A
-
TBD
TBD
A
-
TBD
TBD
A
-
TBD
TBD
A
-
TBD
-
A
Rev.0.10 Jul 20, 2007 REJ03B0219-0010
Page 41 of 44
Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
5. Electrical Characteristics
Timing requirements (Unless Otherwise Specified: VCC = 2.2 V, VSS = 0 V at Topr = 25C) [VCC = 2.2 V] Table 5.28
Symbol tc(XIN) tWH(XIN) tWL(XIN) XIN input cycle time XIN input "H" width XIN input "L" width
XIN Input
Parameter Standard Min. 200 90 90 Max. - - - Unit ns ns ns
tC(XIN) tWH(XIN)
VCC = 2.2 V
XIN input
tWL(XIN)
Figure 5.12
XIN Input Timing Diagram when VCC = 2.2 V
Table 5.29
Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO)
TRAIO Input
Parameter TRAIO input cycle time TRAIO input "H" width TRAIO input "L" width Standard Min. 500 200 200 Max. - - - Unit ns ns ns
tC(TRAIO) tWH(TRAIO)
VCC = 2.2 V
TRAIO input
tWL(TRAIO)
Figure 5.13
TRAIO Input Timing Diagram when VCC = 2.2 V
Rev.0.10 Jul 20, 2007 REJ03B0219-0010
Page 42 of 44
Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
5. Electrical Characteristics
Table 5.30
Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0, 2
Serial Interface
Parameter CLKi input cycle time CLKi input "H" width CLKi input "L" width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Standard Min. 800 400 400 - 0 150 90 Max. - - - 200 - - - Unit ns ns ns ns ns ns ns
tC(CK) tW(CKH)
VCC = 2.2 V
CLKi
tW(CKL) th(C-Q)
TXDi
td(C-Q) tsu(D-C) th(C-D)
RXDi i = 0, 2
Figure 5.14
Serial Interface Timing Diagram when VCC = 2.2 V
Table 5.31
Symbol tW(INH) tW(INL)
External Interrupt INTi (i = 0, 1, 3) Input
Parameter INTi input "H" width INTi input "L" width Standard Min. 1000(1) 1000(2) Max. - - Unit ns ns
NOTES: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater.
VCC = 2.2 V
tW(INL)
INTi input
tW(INH)
i = 0, 1, 3
Figure 5.15
External Interrupt INTi Input Timing Diagram when VCC = 2.2 V
Rev.0.10 Jul 20, 2007 REJ03B0219-0010
Page 43 of 44
Under development
Preliminary specification Specications in this manual are tentative and subject to change
R8C/2K Group, R8C/2L Group
Package Dimensions
Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the "Packages" section of the Renesas Technology website.
JEITA Package Code P-LQFP32-7x7-0.80 RENESAS Code PLQP0032GB-A Previous Code 32P6U-A MASS[Typ.] 0.2g
HD *1
D
24
17 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. bp b1
25
16
HE
E
c1
*2
c
Reference Dimension in Millimeters Symbol
Terminal cross section 32
1 ZD Index mark
8
ZE
9
A2
A
F
A1
L L1
D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1
y e
*3
Detail F bp x
Min Nom Max 6.9 7.0 7.1 6.9 7.0 7.1 1.4 8.8 9.0 9.2 8.8 9.0 9.2 1.7 0.1 0.2 0 0.32 0.37 0.42 0.35 0.09 0.145 0.20 0.125 0 8 0.8 0.20 0.10 0.7 0.7 0.3 0.5 0.7 1.0
Rev.0.10 Jul 20, 2007 REJ03B0219-0010
Page 44 of 44
c
REVISION HISTORY REVISION HISTORY
R8C/2K Group, R8C/2L Group Datasheet R8C/2K Group, R8C/2L Group Datasheet
Description
Rev. 0.10
Date Jul 20, 2007
Page
-
Summary First Edition issued
All trademarks and registered trademarks are the property of their respective owners. C-1
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries.
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
http://www.renesas.com
Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510
(c) 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
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